1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of a dielectric interlayer between and over circuit elements including closely spaced lines, such as gate electrodes, polysilicon interconnect lines and the like.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, MOS technology based on silicon is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost effectiveness. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline silicon layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with a lightly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode that comprises a line-like portion and is formed above the channel region and separated therefrom by a thin insulating layer.
Typically, the circuit elements, such as the MOS transistors, capacitors, resistors and the like, are formed in a common layer, which will be referred to hereinafter as a device layer, whereas the “wiring,” i.e., the electrical connection of circuit elements according to the circuit design, may be accomplished only to a certain degree by means of polysilicon lines and the like within the device layer so that one or more additional “wiring” layers formed over the device layer may be required. These wiring layers include metal lines embedded into an appropriate dielectric material, such as silicon dioxide, silicon nitride and the like, or, in very advanced devices, low-k materials having a permittivity of 3.5 or less are used. The metal lines and the surrounding dielectric material will be referred to hereinafter as a metallization layer. Between two adjacent metallization layers, and also between the device layer and the first metallization layer, respective dielectric interlayers are formed, through which metal-filled openings are formed to establish the electrical connection between metal lines or between circuit elements and metal lines. In typical applications, the dielectric interlayer separating the device layer from the first metallization layer is essentially formed from silicon dioxide that is deposited above a dielectric etch stop layer by well-established plasma enhanced chemical vapor deposition (PECVD) techniques, which enable the formation of a smooth and dense silicon dioxide film with sufficient conformality at moderately high deposition rates. Upon further device scaling resulting in gate lengths of MOS transistors on the order of 50 nm or even less, the distances between neighboring circuit elements, such as polysilicon lines, gate electrodes and the like, are also reduced and have now reached, in modem CPUs, approximately 250 nm and less, which translates into approximately 100 nm or less for the space width between the dense polysilicon lines. It turns out, however, that the gap-fill capabilities of well-established high rate plasma enhanced CVD techniques for the deposition of silicon nitride, which is frequently used as the material for the etch stop layer, and silicon dioxide, which is often used as the interlayer dielectric, may no longer suffice to reliably form a dielectric interlayer, as will be described in more detail with reference to FIG. 1.
In FIG. 1, a semiconductor device 100 comprises a substrate 101 that may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate having formed thereon a device layer 102 including, for instance, a silicon layer 110 having formed thereon a structure 103 that may comprise closely spaced polysilicon lines 104. Hence, the device layer 102 may represent a substantially crystalline silicon region in which and on which circuit elements, such as field effect transistors, capacitors and the like, are formed. The structure 103 may represent an area having a plurality of dense polysilicon lines, or the lines 104 may represent portions of gate electrodes of transistor elements. The lines 104 may have formed on side-walls thereof corresponding spacer elements 105, as are typically used for forming gate electrode structures. The spacer elements 105 may include a plurality of spacers, such as an offset spacer 113 and a liner 112, wherein, typically, the liner 112 and the bulk portion of the spacer 105 are made of different materials. An etch stop layer 109, typically comprised of silicon nitride, is formed over the device layer 102 to cover the layer 110 and the line structure 103. A silicon dioxide layer 107 is formed above the etch stop layer 109 to completely enclose the line structure 103.
A typical conventional process flow for forming the device 100 as shown in FIG. 1 may include the following processes. After fabrication processes to form circuit elements, such as transistors, capacitors and the line structure 103, which include well-established lithography, deposition, etch, implantation and other techniques, the etch stop layer 109 is formed, typically by plasma enhanced chemical vapor deposition (PECVD), since PECVD of silicon nitride may be accomplished at moderately low temperatures of less than approximately 600° C., which is compatible with preceding manufacturing processes and materials, such as metal silicides and the like. As previously discussed, the ongoing shrinkage of feature sizes also entails that a distance between neighboring circuit elements, such as a distance 111 between the closely spaced lines 104, is reduced and may be as low as approximately 100 nm in the 130 nm technology, whereas the distance 111 may be as small as 30 nm and even less for currently manufactured CPUs of the 90 nm technology node. Hence, any deposition techniques for forming a dielectric layer for embedding the line structure 103 with open spaces therebetween have to meet the requirements of an appropriate fill capability to reliably and completely fill the empty spaces between the densely spaced lines 104. By means of well-established PECVD process recipes for silicon nitride, the layer 109 may be deposited in a more or less conformal fashion with a thickness in the range of approximately 10-80 nm. However, owing to the reduced distance 111, the well-established deposition recipes used in the 130 nm technology may not result in a defect-free deposition of the etch stop layer 109 and may instead create voids 106a. 
Thereafter, the silicon dioxide layer 107 is deposited, which is typically done by PECVD on the basis of precursors TEOS (tetra-ethyl-ortho-silicate) and oxygen, since PECVD, contrary to thermal TEOS CVD, allows the deposition of silicon dioxide in a moderately conformal manner (yet with significantly less gap filling qualities compared to thermal CVD) with relatively high mechanical stability at temperatures below 600° C. at high deposition rates, which provides a high production yieid. Moreover, PECVD cluster tools are readily available so that the silicon nitride layer 109 and the PECVD silicon dioxide layer 107 may be deposited in a highly efficient manner.
However, with the distance 111 approaching approximately 30 nm and even less, it turns out that the fill capabilities of well-established PECVD techniques for depositing silicon dioxide on the basis of TEOS and oxygen may not be adequate to completely fill the empty spaces between the lines 104, thereby possibly creating voids 106b, which may, in combination with the voids 106a that may have been created in preceding deposition step(s), lead to severe reliability concerns during the further processing of the semiconductor device 100. Moreover, it should be noted that the silicon dioxide layer 107 has a certain topography caused by the underlying structure of the device layer 102, for instance, by the line structure 103, which may jeopardize subsequent manufacturing processes, such as a photolithography step for forming contact openings to underlying portions of circuit elements located in the layer 110 or on the lines 104. Consequently, a standard process flow requires that the silicon dioxide layer 107 be planarized, typically by chemical mechanical polishing (CMP), wherein excess material of the silicon dioxide layer 107 is removed by chemical and mechanical interaction with a slurry and a polishing pad to finally obtain a substantially planarized surface of the silicon dioxide layer 107. The CMP process itself is a highly complex process and requires sophisticated process recipes, which significantly depend on the characteristics of the silicon dioxide layer 107, such as density, mechanical stress, water contents and the like. Hence, a great deal of effort has been made for the 130 nm technology to develop corresponding process recipes for reliable and reproducible CMP processes for PECVD TEOS silicon dioxide, as this material is frequently used for a dielectric interlayer in silicon-based semiconductor devices and even in devices formed from other semiconductors. As previously noted, the transition to the 90 nm technology may render these process recipes inappropriate due to the insufficient gap fill capabilities.
For this reason, the dielectric layer 107 formed on the silicon nitride layer 109 may be deposited by a different deposition technique having a significantly enhanced gap filling capability to avoid at least the creation of the voids 106b. Hence, the silicon dioxide layer 107 may be formed by a thermal CVD process on the basis of TEOS and ozone, which generates a silicon dioxide film exhibiting excellent gap filling capabilities, that is, this deposition technique provides excellent conformality, and may even display a “flow”-like behavior, thereby allowing reliable filling of the empty spaces between the lines 104. In view of the film characteristics, the thermal CVD process is typically performed at significantly higher pressures compared to the plasma enhanced deposition technique, for example in the range of 200-760 Torrs, and is therefore denoted as “sub-atmospheric CVD” (SACVD). Another deposition technique for silicon dioxide is the plasma enhanced deposition in which a high density plasma is used, thereby also achieving excellent conformality and gap-filling capabilities. After the formation of the silicon dioxide layer 107 in accordance with one of these two deposition techniques, further processing may be continued as is described with reference to FIG. 1. That is, the silicon dioxide layer 107 is planarized by CMP. Despite the superior gap filling capabilities of the SACVD and the high density plasma (HDP) CVD, it turns out that the very different film characteristics of the silicon dioxide layer compared to the PECVD film require completely new CMP and substrate handling strategies and may also bring about a significant reduction in production yield due to reduced deposition rates, particularly when the SACVD technique is employed.
In view of the problems identified above, there exists a need for an efficient technique for forming a dielectric interlayer for the first metallization layer, especially for devices having empty spaces between densely formed lines of approximately 100 nm or less.